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| CYK512K16SCCA MoBL(R) 8-Mbit (512K x 16) Pseudo Static RAM Features * Advanced low-power MoBL(R) architecture * High speed: 55 ns, 70 ns * Wide voltage range: 2.7V to 3.3V * Typical active current: 2 mA @ f = 1 MHz * Typical active current: 11 mA @ f = fMAX * Low standby power * Automatic power-down when deselected Functional Description[1] The CYK512K16SCCA is a high-performance CMOS pseudo static RAM (PSRAM) organized as 512K words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery LifeTM (MoBL) in portable applications such as cellular telephones. The device can be put into standby mode reducing power consumption dramatically when deselected (CE1 LOW, CE2 HIGH or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE1 HIGH, CE2 LOW), OE is deasserted HIGH, or during a write operation (Chip Enabled and Write Enable WE LOW). Reading from the device is accomplished by asserting the Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the Truth Table for a complete description of read and write modes. Logic Block Diagram DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER 512K x 16 RAM Array SENSE AMPS I/O0-I/O7 I/O8-I/O15 COLUMN DECODER BHE WE OE BLE BHE BLE CE2 CE1 CE2 CE1 Note: 1. For best-practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05425 Rev. *E A11 A12 A13 A14 A15 A16 A17 A18 Pow er Down Circuit * 3901 North First Street * San Jose, CA 95134 * 408-943-2600 Revised January 25, 2005 CYK512K16SCCA MoBL(R) Pin Configuration[2, 3, 4] 48-Ball FBGA Top View 4 2 3 1 BLE I/O8 I/O9 VSS VCC I/O14 I/O15 A18 5 A2 CE1 I/O1 I/O3 I/O4 I/O5 WE A11 6 CE2 I/O0 I/O2 VCC VSS I/O6 I/O7 NC A B C D E F G H OE BHE I/O10 I/O11 A0 A3 A5 A17 A1 A4 A6 A7 A16 A15 A13 A10 I/O12 DNU I/O13 NC A8 A14 A12 A9 Product Portfolio[5] Power Dissipation VCC Range (V) Product CYK512K16SCCA Min. 2.7 Typ. 3.0 Max. 3.3 Operating, ICC (mA) Speed (ns) 55 70 f = 1 MHz Typ.[5] 2 Max. 5 f = fMAX Typ.[5] 11 Max. 22 17 Standby, ISB2 (A) Typ.[5] 55 Max. 100 Notes: 2. DNU pins are to be left floating or tied to VSS. 3. Ball G2, H6 are the address expansion pins for the 16-Mbit and 32-Mbit densities respectively. 4. NC "no connect"--not connected internally to the die. 5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC (typ) and TA = 25C. Document #: 38-05425 Rev. *E Page 2 of 10 CYK512K16SCCA MoBL(R) Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied .............................................. -40C to +85C Supply Voltage to Ground Potential ................ -0.4V to 4.6V DC Voltage Applied to Outputs in High-Z State[6, 7, 8] ....................................... -0.4V to 3.7V Range Industrial DC Input Voltage[6, 7, 8] ....................................-0.4V to 3.7V Output Current into Outputs (LOW) ............................ 20 mA Static Discharge Voltage ......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current .................................................... > 200 mA Operating Range Ambient Temperature (TA) -25C to +85C VCC 2.7V to 3.3V DC Electrical Characteristics (Over the Operating Range)[5, 6, 7, 8] CYK512K16SCCA-55 Parameter VCC VOH VOL VIH VIL IIX IOZ ICC Description Supply Voltage Output HIGH Voltage IOH = -0.1 mA Output LOW Voltage IOL = 0.1 mA Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current F=0 GND < VIN < VCC GND < VOUT < VCC, Output Disabled f = fMAX = 1/tRC VCC = 3.3V, IOUT = 0 mA, f = 1 MHz CMOS level 0.8 * VCC -0.4 -1 -1 11 2 100 Test Conditions Min. 2.7 VCC - 0.4 0.4 VCC + 0.4 0.4 +1 +1 22 5 400 0.8 * VCC -0.4 -1 -1 11 2 100 Typ. [5] CYK512K16SCCA-70 Min. 2.7 VCC - 0.4 0.4 VCC + 0.4 0.4 +1 +1 17 5 400 A Typ.[5] Max. 3.3 Unit V V V V V A A mA Max. 3.3 3.0 ISB1 Automatic CE1 CE > VCC - 0.2V, CE2 < 0.2V Power-down Current VIN > VCC - 0.2V, VIN < 0.2V, f = fMAX(Address and Data Only), --CMOS Inputs f = 0 (OE, WE, BHE and BLE) Automatic CE1 CE > VCC - 0.2V, CE2 < 0.2V Power-down Current VIN > VCC - 0.2V or VIN < 0.2V, f = 0, VCC =3.3V --CMOS Inputs ISB2 55 100 55 100 A Capacitance[9] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz VCC = VCC(typ) Max. 8 8 Unit pF pF Thermal Resistance[9] Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. FBGA 55 17 Unit C/W C/W Notes: 6. VIH(MAX) = VCC + 0.5V for pulse durations less than 20 ns. 7. VIL(MIN) = -0.5V for pulse durations less than 20 ns. 8. Overshoot and undershoot specifications are characterized and are not 100% tested. 9. Tested initially and after design or process changes that may affect these parameters. Document #: 38-05425 Rev. *E Page 3 of 10 CYK512K16SCCA MoBL(R) AC Test Loads and Waveforms R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE Parameters R1 R2 RTH VTH R2 VCC GND 10% ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Rise Time = 1 V/ns Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT VTH 3.0V VCC 22000 22000 11000 1.50 Unit V Switching Characteristics (Over the Operating Range) [10, 11, 12, 13, 14] CYK512K16SCCA-55 Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tDBE tLZBE tHZBE tSK[14] Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW and CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z[11, 12] Z[11, 12] Z[11, 12] 5 25 55 5 10 0 5 25 10 5 25 5 25 70 OE HIGH to High 5 55 25 5 25 55[14] 55 5 70 35 70 70 ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. CYK512K16SCCA-70 Min. Max. Unit CE1 LOW and CE2 HIGH to Low BLE/BHE LOW to Data Valid BLE/BHE LOW to Low Z Address Skew [11, 12] [11, 12] CE1 HIGH and CE2 LOW to High Z[11, 12] BLE/BHE HIGH to High-Z Notes: 10. Test conditions assume signal transition time of 1V/ns or higher, timing reference levels of VCC(typ)/2, input pulse levels of 0V to VCC(typ), and output loading of the specified IOL/IOH and 30-pF load capacitance 11. tHZOE, tHZCE, tHZBE and tHZWE transitions are measured when the outputs enter a high-impedance state. 12. High-Z and Low-Z parameters are characterized and are not 100% tested. 13. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, CE2 = VIH, BHE and/or BLE =VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates write. 14. To achieve 55-ns performance, the read access should be CE controlled. In this case tACE is the critical parameter and tSK is satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle. Document #: 38-05425 Rev. *E Page 4 of 10 CYK512K16SCCA MoBL(R) Switching Characteristics (Over the Operating Range) (continued)[10, 11, 12, 13, 14] CYK512K16SCCA-55 Parameter Write Cycle tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE [13] CYK512K16SCCA-70 Min. 70 55 55 0 0 55 55 42 0 Max. Unit ns ns ns ns ns ns ns ns ns 25 5 ns ns Description Write Cycle Time CE1 LOW and CE2 HIGH to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width BLE/BHE LOW to Write End Data Set-up to Write End Data Hold from Write End WE LOW to High WE HIGH to Low Z[11, 12] Z[11, 12] Min. 55 45 45 0 0 40 50 42 0 Max. 25 5 Switching Waveforms Read Cycle 1 (Address Transition Controlled)[14, 15, 16] tRC ADDRESS tSK DATA OUT tOHA tAA DATA VALID PREVIOUS DATA VALID Read Cycle 2 (OE Controlled)[14, 15] ADDRESS tSK tRC CE1 CE2 tACE BHE/BLE tHZCE tLZBE OE tDBE tHZBE DATA OUT tLZOE HIGH IMPEDANCE tLZCE t tDOE DATA VALID tHZOE HIGH IMPEDANCE ICC VCC PU Notes: 15. WE is HIGH for Read Cycle. 16. Device is continuously selected. OE, CE = VIL. Document #: 38-05425 Rev. *E Page 5 of 10 CYK512K16SCCA MoBL(R) Switching Waveforms (continued) Write Cycle No. 1(WE Controlled)[12, 13, 17, 18, 19] tW C ADES D RS tS E C C1 E CE2 C2 E tA W tS A W E tH A tP E W BE L H /B E tB W O E tS D DT A AI/O D 'T C R ON AE tH D VL DT A ID A A tH E ZO Write Cycle 2 (CE1 or CE2 Controlled)[12, 13, 17, 18, 19] tWC ADDRESS tSCE CE1 CE2 tSA tAW tPWE tHA WE tBW BHE/BLE OE tSD DATA I/O DON'T CARE tHD VALID DATA tHZOE Notes: 17. Data I/O is high impedance if OE >VIH. 18. If Chip Enable goes INACTIVE simultaneously with WE = HIGH, the output remains in a high-impedance state. 19. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied. Document #: 38-05425 Rev. *E Page 6 of 10 CYK512K16SCCA MoBL(R) Switching Waveforms (continued) Write Cycle 3 (WE Controlled, OE LOW)[18, 19] tWC ADDRESS tSCE CE1 CE2 BHE/BLE tBW tAW tSA tPWE t HD tHA WE tSD DATAI/O DON'T CARE VALID DATA tHZWE tLZWE Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[18, 19] tC W ADES D RS C1 E C2 E tC SE tW A tW B tA H BE L H /B E tA S W E tW PE tD S D T I/ AA O DN CR O' AE T t HD tH D V LDD T AI AA Document #: 38-05425 Rev. *E Page 7 of 10 CYK512K16SCCA MoBL(R) Truth Table[20] CE1 H X X L L L L L L L L L CE2 X L X H H H H H H H H H WE X X X H H H H H H L L L OE X X X L L L H H H X X X BHE X X H L H L L H L L H L BLE X X H L L H L L H L L H Inputs/Outputs High Z High Z High Z Data Out (I/O0-I/O15) Data Out (I/O0-I/O7); I/O8-I/O15 in High Z Data Out (I/O8-I/O15); I/O0-I/O7 in High Z High Z High Z High Z Data In (I/O0-I/O15) Data In (I/O0-I/O7); I/O8-I/O15 in High Z Data In (I/O8-I/O15); I/O0 -I/O7 in High Z Mode Deselect/Power-down Deselect/Power-down Deselect/Power-down Read (Upper Byte and Lower Byte) Read (Lower Byte only) Read (Upper Byte only) Output Disabled Output Disabled Output Disabled Write (Upper Byte and Lower Byte) Write (Lower Byte Only) Write (Upper Byte Only) Power Standby (ISB) Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 55 70 55 70 Ordering Code CYK512K16SCCAU-55BAI CYK512K16SCCAU-70BAI CYK512K16SCAU-55BAXI CYK512K16SCAU-70BAXI Package Name BA48K BA48K BA48K BA48K Package Type 48-ball Fine Pitch BGA (6.0 x 8.0 x 1.2 mm) 48-ball Fine Pitch BGA (6.0 x 8.0 x 1.2 mm) 48-ball Fine Pitch BGA (6.0 x 8.0 x 1.2 mm) (Pb-Free) 48-ball Fine Pitch BGA (6.0 x 8.0 x 1.2 mm) (Pb-Free) Operating Range Industrial Industrial Industrial Industrial Note: 20. H = Logic HIGH, L = Logic LOW, X = Don't Care Document #: 38-05425 Rev. *E Page 8 of 10 CYK512K16SCCA MoBL(R) Package Diagrams 48-Ball (6 mm x 8mm x 1.2 mm) FBGA BA48K BOTTOM VIEW TOP VIEW A1 CORNER O0.05 M C O0.25 M C A B A1 CORNER 1 2 3 4 5 6 O0.300.05(48X) 6 5 4 3 2 1 A B A B 8.000.10 0.75 C C D E 8.000.10 E F G H 5.25 D 2.625 F G H A B 6.000.10 A 1.875 0.75 3.75 0.25 C 0.530.05 0.210.05 B 6.000.10 0.15 C 0.15(4X) REFERENCE JEDEC MO-207 SEATING PLANE 51-85150-*B 1.20 MAX 0.36 C 51-85193-*A MoBL is a registered trademark, and MoBL3 and More Battery Life are trademarks, of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05425 Rev. *E Page 9 of 10 (c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CYK512K16SCCA MoBL(R) Document History Page Document Title: CYK512K16SCCA 8-Mbit (512K x 16) Pseudo Static RAM Document #: 38-05425 REV. ** *A *B *C ECN NO. Issue Date 130538 216680 220121 230851 01/27/04 See ECN See ECN See ECN Orig. of Change AWK REF REF AJU New Data Sheet Added 55 ns Speed bin Updated from Advance Information to Final Data Sheet. Changed the tOHA for 70 ns speed grade from 10 ns to 5 ns Changed the ISB2 from 80 A to 100 A Changed Ordering code from CYK512K16SCCA to CYK512K16SCCAU in `Ordering Information' table Modified MAX limit on DC Input voltage from 3.3V to 3.7V in `Maximum Ratings' section Changed the tSD write parameter from 25ns to 42ns for both the 55ns and 70ns speed grade. Added Pb-Free parts to the Ordering information Description of Change *D *E 283389 313999 See ECN See ECN REF RKF Document #: 38-05425 Rev. *E Page 10 of 10 |
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